The fabrication of semiconductor devices such as integrated circuits and micro electro-mechanical system (MEMS) devices typically involves multiple processing steps. As part of the fabrication process, a masking process referred to as photolithography or photomasking is used to transfer a pattern onto a semiconductor substrate. Photolithography generally involves reproducing an image from a mask in a layer of photoreactive polymer or photoresist that is supported by underlying layers of a semiconductor substrate. In the photolithography process, an optical mask is positioned between an irradiation source and the photoresist layer. The image is reproduced by exposing the photoresist to light or radiation energy through the optical mask. In a typical semiconductor manufacturing process, an etching process is employed in which the pattern of the photoresist mask layer is etched into underlying layers of the substrate. The layers underlying the photoresist layer generally include one or more layers that are to be patterned. When an etching process is employed in the manufacture of semiconductor devices, the complete removal of photoresist, photoresist residues and other residues and contaminants from the etched surface is desired in order to achieve high yield. The removal of the photoresist, photoresist residue and other residues and contaminants such as residual etching reactants and by products is commonly known as stripping.
One challenge in photolithography is the difficulty of obtaining uniform exposure of the photoresist layer. For example, standing wave patterns (normally incident light forms standing waves because of constructive and destructive interference) and reflective notching can occur due to the optical properties of the layers underlying the photoresist and due to the varying thickness of the photoresist. As shorter wavelengths are being used in the photolithography process to allow patterning of smaller features, interference effects become more pronounced.
As semiconductor device feature sizes decrease with advancing technologies, smaller geometries can require thinner photoresist layers for enhanced depth of focus. It can be desirable to provide a bottom anti-reflective coating (BARC) beneath the photoresist for purposes of minimizing optical reflection of the light used to expose the pattern in the photoresist. The reduction of optical reflection reduces or eliminates the interference patterns of radiation within the photoresist layer. Anti-reflective coatings are generally classified either based on the material used—into inorganic and organic anti-reflective coatings—or based on the operation mechanism—into absorptive and interfering anti-reflective coatings. Organic anti-reflective materials work to prevent reflectivity by matching the refractive index of the anti-reflective material with that of the resist. If there is no difference in the respective refractive indices, then there will be no optical reflection at the photoresist-BARC interface. Some organic anti-reflective materials are designed to absorb light energy passing through the photoresist layer. Absorption is desired to control scattered light energy reflecting from the substrate back up into the photoresist. The use of a BARC layer can improve the photolithography process control by reducing or eliminating standing waves and reflective notching, thereby improving critical dimension control.
High performance, high-density integrated circuits (ICs) can contain tens of millions of transistors. There is a constant push to increase the number of transistors on wafer-based ICs. With the decreasing size of semiconductor devices and an increasing density of transistors, there is a need to prevent undesired capacitive interactions between the adjacent metal lines of the metallization scheme and/or conductive regions of an integrated circuit (commonly referred to as “parasitic capacitance,” “capacitive coupling” or “cross-talk”) in order to allow high-performance signal processing. The semiconductor industry is continually looking for new materials and new processes to improve the performance of wafer-based ICs.
Generally, materials with a dielectric constant (k) of lower than 3.9 are referred to as low-k materials. Porous materials with a dielectric constant of 2.5 and lower are generally referred to as ultra low-k materials. For the purposes of this disclosure, “low-k materials” encompasses both low-k and ultra low-k materials. Low-k materials have been used in advanced ICs to minimize interconnection resistance-capacitance time delays, thereby increasing the speed of signal propagation. Low-k materials have been shown to reduce cross-talk, thereby facilitating the fabrication of smaller feature geometries and more complex micro devices. Low-k materials have been used for low-temperature processing. For example, spin-on glass (SOG) materials and polymers can be coated onto a substrate, such as a semiconductor substrate, and treated or cured under relatively low temperature to form porous silicon oxide-based low-k layers. Dual-damascene processes (techniques for the simultaneous formation of a conductive plug in electrical contact with a conductive line) involving low-k materials are also known. Low-k materials can be deposited on a substrate by any of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin-on techniques. For example, low-k materials such as carbon-doped oxide or fluoridated silicon glass can be formed on a substrate by performing a CVD process, while other low-k materials, such as methyl silsesquioxane (MSQ), porous-MSQ and porous silica, can be deposited using a spin-on process.
FIG. 1 shows a schematic cross-sectional view of a prior art semiconductor device manufacturing method including a BARC (130) layer formed on a conventionally prepared dielectric material (110), which in turn is formed on a semiconductor substrate (100), (not to scale). FIG. 1 also shows a photoresist (150) formed on the BARC (130) layer.
While low-k materials have been used in the fabrication of advanced micro circuitry, the lower density, reduced mechanical properties, and typically increased organic content of low-k materials present fabrication challenges. For example, due to the porosity and higher concentration of carbon in low-k materials, the materials are susceptible to damage by conventional etch and plasma ashing processes. Plasma ashing is the process of removing the photoresist and the etch polymer residues from an etched wafer. In traditional plasma strip processes, a reactive species, such as oxygen or fluorine, combines with the resist to form ash that is removed with a vacuum pump. One problem is that conventional etch and plasma ashing processes can oxidize the carbon within the low-k material itself, altering its k value. For example, porous MSQ film, which is hydrophobic and not susceptible to water absorption, exhibits significant loss of carbon species and suffers increased water absorption and dielectric constant after exposure to ash and wet clean processes. Further, silicon oxide-based low-k materials tend to be highly reactive after patterning steps, such as conventional photolithography. The hydrophilic surface of the silicon oxide-based low-k material can readily absorb water and/or react with other vapors and/or process contaminants, which can alter a dielectric characteristic of the dielectric layer itself and/or diminish the ability to further process the wafer.
There is a need for effective stripping processes to achieve improved device performance with higher productivity and reduced production costs. There is a need for effective stripping processes to completely remove the photoresist and underlying BARC layer, without altering of a dielectric characteristic of a dielectric layer having a low dielectric constant (low-k). There is a need for removing contaminants and particles from a fluid such as carbon dioxide.